1. Introduction
Software AES implementations on microcontroller-class IoT devices often cannot meet both the throughput and energy budgets required for encrypting sensor data streams, motivating compact hardware AES cores implemented on low-cost FPGAs for edge gateway applications.
2. Methodology
An 8-bit datapath AES-128 encryption core was designed in Verilog targeting a Xilinx Artix-7 FPGA, with the substitution-box implemented using composite-field arithmetic in GF((2^4)^2) rather than a conventional 256-entry lookup table, trading combinational logic depth for reduced memory-block usage, and verified against NIST AES test vectors.
3. Results
The composite-field implementation occupied 312 slice LUTs and no block RAM, a 41 percent area reduction compared to a lookup-table-based baseline occupying 528 LUTs plus one BRAM, while achieving an encryption throughput of 34 Mbps at a 100MHz clock, an 18 percent reduction from the 41 Mbps achieved by the lookup-table baseline.
4. Conclusion
Composite-field S-box construction offers a favourable area-throughput tradeoff for AES cores targeting the smallest FPGA fabrics common in IoT edge gateways. Future work will extend the design to support AES-256 and authenticated encryption modes.
References
[1] NIST FIPS 197, Advanced Encryption Standard, National Institute of Standards and Technology, 2001. [2] Rudra A. et al., Efficient Rijndael encryption implementation with composite field arithmetic, CHES, 2001.